Jacqueline Radding

Electrical Engineer | Cal Poly Master's Student | Cal Poly IEEE President

About Me

Jacqueline Radding

Hello! I'm Jacqueline Radding, a Master's student in Electrical Engineering at Cal Poly San Luis Obispo. I specialize in PCB design and digital communications. Alongside my studies, I serve as the President of Cal Poly IEEE and work as a Resident Advisor, mentoring fellow students. My passion lies in developing IOT technologies and advancing research in V2V communication systems.

Experience & Publications

Development of a Laboratory Course in Industrial Power and Control (2023)

Publication: ASEE PSW Conference 2024, Las Vegas, NV.

This paper discusses the design and implementation of an industrial power and control lab for Electrical Engineers.

Texas Instruments Internship: Automated Voltage Spike Checker (2024)

Designed and automated PCB tests, reducing manual labor by 50% and improving program efficiency.

Hewlett Packard Enterprise: FCC compliance Simulation (2023)

Simulated radiated emissions and implemented solutions to achieve FCC compliance in hybrid cloud products.

Master Thesis (In Progress): Connected Autonomous Vehicles(2024/2025)

Harmonizing motion and communication using machine learning to optimize V2V digital communication systems.

Projects

Transmitting Images Over SDRs With GNU Radio and Simulink

Used raspberry pi SDRs to compare different modulation schemes(BPSK, QPSK, 16QAM) to find the maximum distance they could send an image to another SDR using GNU Radio and Simulink. First image is sending an image over air to another SDR using BPSK Second image is sending an image over air to another SDR using 16QAM (Not performing well because of the smaller decision boundaries) Third and fourth images are the code flow diagrams of the transmitter and receiver

Additional Resources: Download Lab Notebook (PDF) Download SDR Modulation Final Report (PDF)

10 MHz Low Pass Filter Simulation

Here is a 10 MHz low pass filter built in Keysight ADS. The filter was ordered on Oshpark PCB and had its S-parameters magnitude and phase tested on a VNA. Impedance was also tested. Use the arrows below to navigate through the simulation and results images.

Additional Resources: Download Full Project Details (PDF)

Simulink Costas Loop BPSK

A receiver was designed to synchronize and demodulate 10 kbps data modulated using BPSK with a nominal 200 kHz carrier. The transmitter consistently begins with a pilot signal consisting of ten consecutive '1' bits, followed by the data stream. In the first image, a test harness is shown with configurable parameters, allowing adjustments to phase, frequency, and angle drift. The second image illustrates a Costas loop, implemented to correct frequency bias and phase offset. The Costas loop locks onto the signal’s center frequency, downconverting it to baseband by generating a local, in-phase replica of the carrier, multiplying it with the received signal, and then filtering the result through a low-pass filter. The third image depicts a voltage-controlled oscillator (VCO) that generates a local carrier signal aligned with the phase of the received signal. The fourth image shows a sample-and-hold system designed to detect the pilot signal, triggering the receiver to process the incoming data once the pilot is successfully identified.

Blog

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Contact

Feel free to reach out to me for collaborations, questions, or networking!

Email: [email protected]

Portfolio: My Portfolio